23rd International Symposium on VLSI Design and Test (VDAT-2019)

July 4 - 6, 2019

Theme of VDAT 2019:

Chip to System Design for Artificial Intelligence based Systems

Keynote Speakers
Tutorial Speakers
Startup Speakers
WiE Speakers
Shri Govindram Seksaria Institute of Technology and Science, Indore
All the accepted papers will be published by Springer

About VDAT 2019

VDAT began as a small workshop in the year 1998. In 2005, it acquired the status of a Symposium. The purpose of the Symposium is to promote the advancement of all aspects of VLSI. The 23rd International Symposium on VLSI Design and Test (VDAT-2019) is being held in Indian institute of Technology Indore, India. The aim of this symposium is to bring academics, researchers, startups and industrial practitioners together to exchange their ideas in the area of VLSI design, test and system design.

About Indore

Indore is a fascinating city with a blend of a rich cultural and historical heritage hosting a wide range of styles of the Maratha, Mughal, Holkar and British era. Chhatris, Laal Bag Palace, Kanch Mandir are cues of its architectural exellence. Situated on one of India's oldest pilgrimage routes from Mahakaal at Ujjain on river Kshipra, to Omkareshwar on the river Narmada and onwards to Rameshwaram, Indore is embellished by several forts and rocky shrines: Mandu, Dewas, Maheshwar, Omkareshwar being the prominent ones. One of the most legendary rulers of Indian history, Devi Ahilyabai Holkar is the patron of many traditional architecture here. Apart from these, the rustic spirit of Chokhi and Nakhrali Dhani, heritage resorts on the outskirts of Indore filled with varied traditional Rajasthani delicacies adds a Rajasthani flavour to the city. Gujarati and Marathi cultures also have influenced life in Indore. Being situated in the heart of India, Indore has excellent air and rail connectivities with the metro cities namely Mumbai, Kolkata, Delhi, Hyderabad, Bangalore and many more. Places like Agra, Jaipur, Udaipur, Ajanta-Ellora caves are in its vicinity. Agra, our city of pride entails the 8th Wonder, white marble mausoleum, Taj Mahal. It is a universally admired masterpieces of the world's heritage.

About IIT Indore

IIT Indore located at Simrol, Khandwa Road, Madhya Pradesh, is one of the eight new Indian Institutes of Technology (IIT) established by the Ministry of Human Resource Development (MHRD), Government of India in 2008-09. Recently IIT Indore is ranked 14th amongst all engineering universities and institutions in India and a very impressive 5th in teaching and resource category by MHRD as per NIRF 2018 and IIT Indore debuts with a rank of 351-400 in the Times Higher Education World University Rankings 2019, 2nd amongst Indian Institutes.. IIT Indore, established in 2009 by the Government of India, is a unique educational institution that focuses on interdisciplinary research and teaching. The institute is growing rapidly as the only center for advanced learning and knowledge-dissemination in the pure and applied sciences in Central India. The interdisciplinary approach of the institute is well reflected in its departmental setup comprising basic sciences, a school of engineering and a school of social sciences. The larger commitment of the institute to socio-economic development is evident in its multi-dimensional approach to social problems and is engraved in its motto ('knowledge for the well being of all'), which makes this institution one of its kind and it stands out even within the distinguished IIT family.

VDAT 2019, Program Schedule

Venue: Hotel Radisson, Indore

Time Day 1: July 4, 2019 (Thursday)
08:00-09:00 Registration
(Ground floor, Hotel Radisson)
09:00-09:45 Inauguration
(Grand Summit Hall, Ground Floor)
Grand Summit Hall, Ground Floor
Summit Hall - I Summit Hall - II
09.45-11:00 Bedanta Choudhury
Nishit Gupta
Meity Govt. of India
11:00-11:15 Tea Break
11:15-12:15 Prashant Admane
Tessolve Semiconductor
Amit Chhabra
12:15-13:00 Lunch Break
13:00-14:15 Bhupendra Vishvakarma and
K V N Savan K, Intel
Ramesh Devani
14:15-14:30 Tea Break
14:30-15:30 TBA Sandeep Bhattacharya
ST Microelectronics
Startup Forum
Summit Hall - I
Nilesh Trivedi, MSME, Govt. of India
Ashok Mishra, ALTEN Calsoft Labs
H.S. Jatana, SCL
Puneet Mittal, VLSI Expert
Himalayan Bansal, LDRA
Time Day 2: July 5, 2019 (Friday)
09:00-10:00 Keynote - I
Jaydeep Kulkarni, University of Texas at Austin
(Grand Summit Hall , Ground floor)
Paper Presentation
10:00 – 11:30 Session I
Summit Hall - I
Session II
Summit Hall – II
11:30 -12:00 Tea Break and Poster Exhibition
12:00-13:00 Session III
Summit Hall - I
Session IV
Summit Hall – II
13:00-14:00 Lunch Break
14:00-15:00 Keynote –II
Soft Error in Chips and Systems
Krishnan Rengarajan, Cypress Semiconductor
(Grand Summit Hall , Ground floor)
Paper Presentation
15:00-16:00 Session V
Summit Hall - I
Session VI
Summit Hall – II
16:00- 16:15 Tea Break
Women in Engineering (WiE),
Summit Hall - I
Sunita Verma, Meity, Govt. of India
Suman Dwivedi, Globalfoundries
Sampada A. Deshpande, Cadence
Namerita Khanna, ST Microelectronics
19:00- 23:00 Award Ceremony, Culture Event and Banquet Dinner
Time Day 3: July 6, 2019 (Saturday)
09:00-10:00 Keynote - III
Preeti Ranjan Panda, IIT Delhi
(Grand Summit Hall , Ground floor)
Paper Presentation
10:00 – 11:30 Session VII
Summit Hall - VIII
Session II
Summit Hall – II
11:30 -11:40 Tea Break
11:40-13:10 Session IX
Summit Hall - I
Session X
Summit Hall – II
13:10-14:00 Lunch Break
14:00-15:00 Keynote –IV
Sreekant Prudvi, Avera Semiconductor
(Grand Summit Hall , Ground floor)
Paper Presentation
15:00-16:30 Session XI
(Track: Digital VLSI Design)
Summit Hall - I
Session XII
(Track: Digital VLSI Design)
Summit Hall – II
16:30- 16:45 Tea Break
16:45-17:45 Panel Discussion
17:45-18:15 Conference Valedictory and Award Distribution

Call For Papers

Researchers, academicians and professionals are invited to submit papers in the following topics (but not limited to)

Devices Modeling and Emerging Devices/Material Technologies

MOS Device Modeling and Simulation; Multi-gate and other Emerging MOS devices. Si-Photonics and Optoelectronics devices; MEMS/NEMS; Organic electronics; 2D and advanced material electronics; Flash memory devices and other emerging memory technologies ReRAM, PCM, SSTRAM etc.

VLSI Circuit and System Design

Low power, High-performance and robust design of logic, memory, analog, RF and FPGA circuits; Clock-generation and distribution circuits including alldigital PLLs and DLLs; ADC's and DAC's; Soft-error and fault-tolerant circuits; Circuit design for reliability effects such as gate oxide integrity, electro-migration, ESD, HCI, NBTI, PBTI etc.; On-chip process, voltage, temperature, and aging sensors and monitoring; Hardware accelerators for machine learning (ML) and deep learning algorithms; Hardware implementations of ML algorithms for applications like image/object recognition, computer vision, Speech recognition, and natural language processing; ML-based intelligence in IoT under highly constrained energy/power requirements; Secure and intelligent system on chip (SoC) design for automotive, health and defense applications.

CAD for VLSI and Hardware Security

Logic and behavioral synthesis; Placement, Routing and Floor planning; CAD tools; Design automation; Hardware attacks-detection; Threat modeling & defense; Hardware-based security primitive design; Trusted design automation, Tools & Information flow.

Testing and Verification

Design verification, Test, Reliability and Fault tolerance; Formal verification; DFT; Fault modeling; Post-silicon validation; Testing memories and regular logic arrays; Design for manufacturability and yield analysis.

FPGA based Design and Embedded Systems

FPGA based combinational/sequential logic/circuit design, Hardware/Software co-design and verification; Audio, Image and video processing; Reconfigurable systems; Microcontroller, IoT and FPGA based embedded systems design; Embedded software; CAD for embedded systems; Artificial intelligence and ML based systems.

Submission Instructions

Soft copies of papers should be submitted in .pdf format as per the IEEE conference paper format, submits not exceeding six A4 size pages and paper should be uploaded through easy chair portal. There will be double blind review of the paper. Therefore do not include authors’ name in submitted paper. A Paper with authors’ names will not be considered for review. The paper must include an abstract of about 250 words and maximum of five keywords. The acceptance of the paper is based on the following factors: The purpose of the work; the manner and degree to which it advances the art; specific new results that have been obtained and their significance. Authors of the accepted papers will be informed by email. Information about necessary revisions will be communicated to the corresponding author through email. The author(s) will have to incorporate the suggestions and will have to send the revised camera ready copy of the paper in the given time limit. Along with the paper, authors are required to submit an undertaking form stating that, the paper has not been published previously, is not under consideration for publication elsewhere, and if accepted will not be published elsewhere in the same form. It is mandatory for at least one of the authors to register in non-student category for publication of the paper in proceedings. For the author presenting more than one papers, it is mandatory to register and present each paper separately.

Submission Link:


Important Dates:
  • Regular Papers
    • Full Paper Submission: March 16, 2019 March 31, 2019
    • Notification of Acceptance: May 1, 2019 May 15, 2019
    • Camera Ready Paper: May 1, 2019 May 25, 2019 June 10, 2019
  • Tutorials
    • Tutorial Proposal Submission: March 18, 2019 April 30, 2019
    • Tutorial Announcement: April 15, 2019 May 31, 2019
  • Student Research
    • Full Paper Submission: April 2, 2019 May 2, 2019
    • Notification of Acceptance: April 25, 2019 May 25, 2019
    • Camera Ready Paper: April 30, 2019 May 30, 2019 June 10, 2019
  • Design Contest
    • Submission of Design: April 22, 2019 May 07, 2019
    • Notification of Acceptance: May 15, 2019 May 31, 2019

Download Call For Papers(CFP)


Student Research Forum:

Students, including bachelors, masters and PhDs may participate in this forum through presenting their work for better technical inputs to improve the quality of work. This forum may also provide an opportunity to the students to establish the network with industry players for job perspective.

Startup Forum:

This forum will provide the opportunities to participants to aware the various schemes/initiatives taken by several states and central government in Chip Fabrication, Electronics Manufacturing Clusters (EMC), IoT, ML and AI etc. The forum will also provide a platform to the participants to explore the funding opportunities from venture capitalist, by presenting their ideas.

Women in Engineering Forum:

The forum will provide the opportunities to the participants to accelerate the present engagement in the area of chip design and autonomous embedded systems

Our Commitee

  • Advisory Committee
    • V. Agrawal, Auburn University, USA
    • V. Ramgopal Rao, IIT Delhi, India
    • Satya Gupta, Senzop, Bangalore, India
    • Jaswinder Ahuja, Cadence, Noida, India
    • Anirban Sengupta, IIT Indore, India
    • M. Huebner, BTU, Cottbus, Germany
    • A. Bharadwaj, IISc Bangalore, India
    • Santanu Chaudhury, IIT Jodhpur, India
    • Niranjan Pol, Seagate, Pune, India
    • Roy P. Paily, IIT Guwahati, India
    • Milos Krstic, IHP, Germany
    • Manoj S Gaur, IIT Jammu, India
    • Surindra Singh, SCL, Mohali, India
    • Sunita Verma, MeitY, New Delhi, India
  • General Chairs
    • S. K. Vishvakarma, IIT Indore, India
    • Anirban Sengupta, IIT Indore, India
  • Program Chairs
    • Virendra Singh, IIT Bombay, India
    • Sudeb Dasgupta, IIT Roorkee, India
    • Rohit Sharma, IIT Ropar, India
  • Tutorial Chairs
    • Shailesh Singh Chouhan, Lulia University, Sweden
    • Ashish Kumar, STMicroelectronics, India
    • Ram Bilas Pachori, IIT Indore, India
  • Publicity Chairs
    • Akash Kumar, TU Dresden, Germany
    • Shaibal Mukherjee, IIT Indore, India
    • Bhuvan B., NIT Calicut, India
  • Publication Chairs
    • Brajesh K. Kaushik, IIT Roorkee, India
    • Mukesh Kumar, IIT Indore, India
    • Jai Gopal Pandey, CEERI, Pilani, India
  • Student Research Chairs
    • Srivathsan Vasudevan, IIT Indore, India
    • Linga R. Cenkeramaddi, UiA, Norway
    • M. Anbarasu, IIT Madras, India
  • Fellowship Chairs
    • Gaurav Trivedi, IIT Guwahati, India
    • Ramesh Vaddi, NUS, Singapore
    • Hitesh Shrimali, IIT Mandi, India
  • Sponsorship Chairs
    • S. K. Vishvakarma, IIT Indore, India
    • Ajay Kumar Kushwaha, IIT Indore, India
    • Vivek Kanhangad, IIT Indore, India
  • Industry Chairs
    • Jatinder Singh, IMEC, Bangalore, India
    • Preet Yadav, Wipro, Bangalore, India
    • Devesh Dwivedi, Globalfoundries, India
  • Exhibition Chairs
    • V. Neema, IET, DAVV, Indore, India
    • Abhinoy Kumar Singh, IIT Indore, India
    • Dheeraj Sharma, IIITDM, Jabalpur, India
  • Women in Engineering Chairs
    • Sangeeta Nkhate, MANIT, Bhopal, India
    • Joycee Mekie, IIT Gandhinagar, India
    • Trapti Jain, IIT Indore, India
  • Startup Chairs
    • A. Srivastava, ABVIIITM Gwalior, India
    • Vimal Bhatia, IIT Indore, India
    • Himalya Bansal, AutoCiG, IESA, India
  • Design Contest Chairs
    • R. S. Gamad, SGSITS, Indore, India
    • Ravi Sindal, IET-DAVV, Indore
    • Kailash Chandra Ray, IIT Patna, India
  • Website Chairs
    • Vipul Singh, IIT Indore, India
    • Balwinder Raj, NIT Jalandhar, India
    • Shree Prakash Tiwari, IIT Jodhpur, India

Our Sponsors

Technically Supported by

IEEE Consumer Electronics Society Bombay Chapter

Benefits of Sponsorship

Platinum sponsor

Company logo (large size-main highlight) on VDAT-2019 website, brochure & Front page of Abstract Booklet • Free Registration and accommodation for 2 persons. • Stall for demonstration of company products & technology development • Company logo in main banner+ dining area during all three days of symposium.

Gold Sponsor

Company logo (medium size) on VDAT-2019 website & Back side of cover page (main highlight) on Abstract Booklet. • Free Registration and accommodation for 2 persons. Stall for demonstration of company products & technology development.

Silver Sponsor

Company logo (small size) on VDAT-2019 website & Back side of cover page on abstract. • Free Registration and accommodation for 1 person. • Stall for demonstration of company products & technology development.

Delegate Kit Company logo on VDAT-2019 website, on second page of Abstract Booklet & Symposium bag.

Technical Session Sponsorship

Company logo on VDAT-2019 website, Abstract Booklet (at first page of the particular technical session) & Banner During particular technical session.

Advertisement in Conference Proceeding /Banners

Particulars Amt. in Rs.
Platinum sponsor 3,00,000/-
Gold Sponsor 2,00,000/-
Silver Sponsor 1,00,000/-
Delegate Kit 50,000/-
Technical Session Sponsorship (Per Session) 30,000/-
Banner-Prime location (main stage and dining area) 10,000/-
Banner- Other location 5,000/-

Mode of Payment

Online Transfer/DD/Cheque in favour of The Registrar, Indian Institute of Technology Indore
Name of the Bank CANARA Bank, IIT Indore Campus, Simrol, Indore
Bank Account Number 1476101027440
IFSC Code CNRB0006223
MICR code 452015003

Register Now!


Exhibition Info

A limited number of exhibit stalls of size 3m x 3m will be available where products can be demonstrated. The stalls will come with a power plug and fascia. The exhibitor is expected to make arrangements for any computers or other equipment that may be needed towards the exhibit stall.

The cost of a booth will be Rs 40,000/- per stall.

For Booking Contact:

Dr. Vaibhav Neema
Email : vneema [at] ietdavv.edu.in
Mobile: +91-9174738874

Speakers of Conference

Keynote Speakers

Dr. Jaydeep Kulkarni

Department of Electrical and Computer Engineering,
University of Texas at Austin

Dr. Kulkarni is an assistant professor and holds the AMD endowed chair in computer engineering in the Department of Electrical and Computer Engineering at The University of Texas at Austin.  He received the Ph.D. degree from Purdue University in 2009. During 2009-2017, he worked as a Senior Staff Research Scientist at Intel Labs in Hillsboro, OR. He has filed 35 patents, published 2 book chapters, and 70 papers in referred journals and conferences. His research is focused on energy efficient digital, memory, and power management circuits, emerging nanotechnology applications, and data intensive hardware accelerators. 

Dr. Preeti Ranjan Panda

Professor, Department of Computer Science Engineering,
IIT Delhi

Dr. Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine. He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, and the Advanced Technology Group at Synopsys Inc., Mountain View, and has been a visiting scholar at Stanford University. His research interests are: Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design.

Mr. Krishnan Rengarajan

Technical Lead
Cypress Semiconductor private Limited

Krishnan Rengarajan is an analog Mixed Signal Circuit Design Professional and Technical Lead responsible for IP design across multiple domains: Memories–volatile and non-volatile, High Speed Serial Links, Clock chips and supporting IP - in embedded & discrete chip contexts. He has built teams and delivered on several products/IP through production at Cypress Semiconductor, Globalfoundries, IBM, Edison (IDC of Elpida Inc, Japan), Texas Instruments, TVSElectronics, IITM, DCM Microelectronics. Currently he is Sr.MTS at Cypress Semiconductor. Earlier positions include DMTS at GF, STSM at IBM, Director at Edison and MGTS at TI. His research interests are Low power High speed Signaling and Analog Behavioral modeling. Krishnan got his ME ( Microlectronics) in 1991 and BE(Hons.) EEE in 1989 both from BITS, Pilani.

Mr. Venkatasreekanth (Sree) Prudvi

Venkatasreekanth (Sree) Prudvi received his Masters(M.Sc) in Chemistry and B.E (Hons) degree from Birla Institute of Technology & Science (BITS), Pilani, India. He is been with semiconductor industry for 19 years working for hardware development. He is currently a Distinguished Member of Technical Staff (DMTS) at AveraSemi (a subsidiary of GlobalFoundries), Bangalore. His expertise includes High Speed SerDes (HSS) IP/Testchip development and methodology enablement for ASIC business. Sree has experience of delivering 50+ Testchips that hosted High Speed SerDes IPs. Sree has been recognized for 6 patent disclosures and 11 defensive publications.

Tutorial Speakers

Mr. Ramesh Devani

Technical Manager,
Einfochips Private Limited (An Arrow company), Ahmedabad

R. Devani is presently working as a Technical Manager, in eInfochips private limited (An Arrow company), Ahmedabad. He received his BTech degree in Mechatronics Engineering from GCET college of Engineering and technology, Vallabh Vidhyanagar in 2005. Also completed 6 Month PGDM certification course form Vedant Semiconductor complex limited, Gurgaon in March 2006. He has started his carrier with STMicroelectronics. He also have experience of working on Dual core and Quad core CortexA9 Subsystem on timing and power critical SOC. He has authored/co-authored more than 10 research papers/Articles in peer reviewed international journals and conferences. He is actively engage in bridging gap between industry and academia in Gujarat. 

Dr. Nishit Gupta

R&D in Electronics Group
Ministry of Electronics and Information Technology, Govt. of India

Contact Info


Indian Institute of Technology Indore, Khandwa Rd, Simrol, Madhya Pradesh 453552


Dr. N. K. Yadav
Conference Manager