Indian Institute of Technology Indore
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| Industry Invited Speakers |
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| Women in Engineering (WiE) Speakers |
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| KNOWLEDGE PARTNER |
Shri Govindram Seksaria Institute of Technology and Science, Indore |
| SYMPOSIUM VENUE |
Hotel Radisson BLU, Indore |
| SPONSORS |
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| QUICK LINKS |
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Register Fellowship Holders Important Dates |
| TECHNICAL SUPPORT |
IEEE Consumer Electronics Society Bombay Chapter |
VDAT began as a small workshop in the year 1998. In 2005, it acquired the
status of a Symposium. The purpose of the Symposium is to promote the
advancement of all aspects of VLSI. The 23rd International Symposium on
VLSI Design and Test (VDAT-2019) is being held in Indian institute of
Technology Indore, India. The aim of this symposium is to bring academics,
researchers, startups and industrial practitioners together to exchange their
ideas in the area of VLSI design, test and system design.
Indore is a fascinating city with a blend of a rich cultural and historical heritage hosting a wide range of styles of the Maratha, Mughal, Holkar and British era. Chhatris, Laal Bag Palace, Kanch Mandir are cues of its architectural exellence. Situated on one of India's oldest pilgrimage routes from Mahakaal at Ujjain on river Kshipra, to Omkareshwar on the river Narmada and onwards to Rameshwaram, Indore is embellished by several forts and rocky shrines: Mandu, Dewas, Maheshwar, Omkareshwar being the prominent ones. One of the most legendary rulers of Indian history, Devi Ahilyabai Holkar is the patron of many traditional architecture here. Apart from these, the rustic spirit of Chokhi and Nakhrali Dhani, heritage resorts on the outskirts of Indore filled with varied traditional Rajasthani delicacies adds a Rajasthani flavour to the city. Gujarati and Marathi cultures also have influenced life in Indore. Being situated in the heart of India, Indore has excellent air and rail connectivities with the metro cities namely Mumbai, Kolkata, Delhi, Hyderabad, Bangalore and many more. Places like Agra, Jaipur, Udaipur, Ajanta-Ellora caves are in its vicinity. Agra, our city of pride entails the 8th Wonder, white marble mausoleum, Taj Mahal. It is a universally admired masterpieces of the world's heritage.
IIT Indore located at Simrol, Khandwa Road, Madhya Pradesh, is one of the eight new Indian Institutes of Technology (IIT) established by the Ministry of Human Resource Development (MHRD), Government of India in 2008-09. Recently IIT Indore is ranked 14th amongst all engineering universities and institutions in India and a very impressive 5th in teaching and resource category by MHRD as per NIRF 2018 and IIT Indore debuts with a rank of 351-400 in the Times Higher Education World University Rankings 2019, 2nd amongst Indian Institutes.. IIT Indore, established in 2009 by the Government of India, is a unique educational institution that focuses on interdisciplinary research and teaching. The institute is growing rapidly as the only center for advanced learning and knowledge-dissemination in the pure and applied sciences in Central India. The interdisciplinary approach of the institute is well reflected in its departmental setup comprising basic sciences, a school of engineering and a school of social sciences. The larger commitment of the institute to socio-economic development is evident in its multi-dimensional approach to social problems and is engraved in its motto ('knowledge for the well being of all'), which makes this institution one of its kind and it stands out even within the distinguished IIT family.
| Time | Day 1: July 4, 2019 (Thursday) | |
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| 07:45-08:30 | Registration (Summit Hall, Ground Floor) | |
| 08:30-08:40 | Inauguration (Summit Hall - I) Address by Prof. Pradeep Mathur, Director, IIT Indore |
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| 08:40-08:50 | Address by General Chair, VDAT-2019 | |
| 08:50-09:00 | Address by Technical Program Chair, VDAT-2019 | |
| 09:00-09:40 | Inaugural Talk on Initiatives in Electronics System Design and Manufacturing (ESDM) Space Summit Hall - I Nishit Gupta Ministry of Electronics and Information Technology (MeitY), Govt. of India |
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| 09:40-10:00 | Tea Break | |
| Industry Invited Talks | ||
| Summit Hall - I Chair: Ashish Kumar, ST Microelectronics |
Summit Hall - II Jatinder Singh, IMEC | |
| 10:10-10.50 | Next Generation IoT and Automotive SoC Design: Challenges and Opportunities Bedanta Choudhury NXP Semiconductors |
Virtual Prototyping of System on Chip (VSoC) using Transaction Level Modeling Nishit Gupta and Deepak Jharodia Meity Govt. of India |
| 10:50-11:40 | FPGA and Adaptive Compute Acceleration Platform for AI Applications Vaibhav Kale, Xilinx |
Who's Driving? The Responsibilities that come with Providing Physical IP to the Automotive Market Amit Chhabra ARM |
| 11:40-12:30 | Industry 4.0 Myths Preet Yadav Wipro Limited |
Functional Safety in Automotive Applications Amit Agarwal nVIDIA |
| 12:00-13:10 | Lunch Break | |
| Summit Hall - I Chair: Pooran Singh, Intel |
Summit Hall - II Chair: Soumen Bhattacharya, Intel |
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| 13:10-14:00 | Design Automation in Custom Layout Design Prashant Mathur, Bhupendra Vishvakarma and K V N Savan K Intel |
Advancement and New Trends in DFX Domain to Catereeds of Semiconductor Industry Ramesh Devani einfochips |
| 14:00-14:50 | Analog and Mixed Signal Trends in SoC Development Prashant Admane, Tessolve Semiconductor |
Automotive Functional Safety using Self-Test Mechanism like LBIST and MBIST Sandeep Bhattacharya ST Microelectronics |
| 14:50-15:40 | Embedded Deep Learning for Energy Constrained Systems Manuj Ayodhyawasi ST Microelectronics |
22FDX Technology - Ultra Low Power Design Solution for AI Application Suman Dwivedi Globalfoundries |
| 15:40-16:00 | Tea Break and Poster Session | |
| 16:00-17:00 | Panel Discussion on Smart Electric Vehicles: Opportunities and Challenges for India in the Coming Decade Summit Hall - I Moderator: Amardeep Punhani, NXP Semiconductor Panelist Nishit Gupta, MeitY; Bedanta Choudhury, NXP Semiconductors; Himalya Bansal, LDRA Technology; |
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| 17:00-18:00 | ||
| Startup Session, Summit Hall - I Chair: Prashant Admane, Tessolve Semiconductor |
Round Table Meeting on How can Academia and Industry join Hands to Foster Automotive Electronics Ecosystem in India? Summit Hall - II |
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| Scheme of DCMSMEE and MSME Sector of India Nilesh Trivedi MSME, Govt. of India |
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| Development of SOI-CMOS Technology: Issues and Challenges H.S. Jatana SCL |
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| Startup in Education Field: Challenges and Opportunities Puneet Mittal VLSI Expert |
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| Time | Day 2: July 5, 2019 (Friday) | |
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| 09:00-10:00 | Keynote - I ((Summit Hall - I)) Energy Efficient Embedded Memories in Advanced CMOS: Trends and Prospects Jaydeep Kulkarni, University of Texas at Austin, USA Chair: Anirban Sengupta, IIT Indore |
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| Paper Presentation | ||
| 10:00 – 11:30 | Session I Summit Hall - I Chair: Sandeep Bhattacharya, ST Microelectronics |
Session II Summit Hall – II Chair: Bhupendra Vishvakarma, Intel |
| 11:30 -12:00 | Tea Break and Poster Session | |
| 12:00-13:00 | Session III Summit Hall - I Vaibhav Neema, IET- DAVV, Indore |
Session IV Summit Hall – II Chair: Jai Gopal Pandey, CEERI Pilani |
| 13:00-14:00 | Lunch Break | |
| 14:00-15:00 | Keynote –II (Summit Hall-I) Soft Error in Chips and Systems Krishnan Rengarajan, Cypress Semiconductor Chair: Ambika Prasad Shah, TU Vienna, Austria |
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| Paper Presentation | ||
| 15:00-16:00 | Session V Summit Hall - I Chair: Prashant Admane, Tessolve Semiconductor |
Session VI Summit Hall – II Chair: Ram Rakesh Jangir, RGGP, Jind |
| 16:00- 16:15 | Tea Break | |
| 16:15-17:45 | ||
| Women in Engineering (WiE) Session, Summit Hall - I Panel Discussion on Empowering Women: A Socio-Corporate Perspective Chair: Sangeeta Nakhate, MANIT Bhopal |
VDAT-2020 Meeting 16:15-17:15 Summit Hall - II |
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| Sunita Verma, Meity, Govt. of India | ||
| System Reliability Challenges - ESD/US and Why Point to Point Resistance of ESD Network is Important? Sampada A. Deshpande, Cadence |
Paper Presentation of Student Research Forum (SRF) 17:15-18:00 Chair: Bhupendra Reniwal UST Global Summit Hall - II |
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| Namerita Khanna, ST Microelectronics |
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| 19:30-23:00 | Award Ceremony & Banquet Dinner at Hotel WoW, Indore | |
| Time | Day 3: July 6, 2019 (Saturday) | |
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| 09:00-10:00 | Keynote - III System Architectures and Machine Learning – hype or HYPE? Preeti Ranjan Panda, IIT Delhi (Summit Hall - III) Chair: Virendra Singh, IIT Mumbai |
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| Paper Presentation | ||
| 10:00 – 11:30 | Session VII Summit Hall - III Chair: Amandeep, NIT Srinagar |
Session VIII Summit Hall – IV Chair: Ajai Kushwaha, IIT Indore |
| 11:30 -11:40 | Tea Break | |
| 11:40-13:00 | Session IX Summit Hall - III Chair: Vishal Sharma, Synopsys |
Session X Summit Hall – IV Chair: R. S. Gamad, SGSITS Indore |
| 13:00-13:40 | Lunch Break | |
| 13.40-14.40 | Keynote –IV 4C's of AI Sreekant Prudvi, Avera Semi (Summit Hall - III) Chair: Sudeb Dasgupta, IIT Roorkee |
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| Paper Presentation | ||
| 14:40-16:00 | Session XI Summit Hall – III Chair: Sandeep Bhattacharya, STMicroelectronics |
Session XII Summit Hall – IV Chair: Mukesh Kumar, IIT Indore |
| 16:00- 16:15 | Tea Break | |
| 16:15-17:15 | Panel Discussion on “Chip to System Design for Artificial Intelligence based Systems: A Joint Ecosystem of Academia and Industry in India” Summit Hall – III Moderator: Devesh Dwivedi, Samsung Panelist Soumen Bhattacharya, Intel; Saket Chauhan, Xilinx; Jatinder Singh, IMEC, Sudeb Dasgupta, IIT Roorkee; Prashant P.Bansod, SGSITS Indore; Rakesh Arya, MPCST, Bhopal |
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| 17:15-18:00 | Valedictory Function: Award and Certificate Ceremony Summit Hall – III |
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| Regular Papers Summit Hall – I & II |
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Researchers, academicians and professionals are invited to submit papers in the following topics (but not limited to)
MOS Device Modeling and Simulation; Multi-gate and other Emerging MOS devices. Si-Photonics and Optoelectronics devices; MEMS/NEMS; Organic electronics; 2D and advanced material electronics; Flash memory devices and other emerging memory technologies ReRAM, PCM, SSTRAM etc.
Low power, High-performance and robust design of logic, memory, analog, RF and FPGA circuits; Clock-generation and distribution circuits including alldigital PLLs and DLLs; ADC's and DAC's; Soft-error and fault-tolerant circuits; Circuit design for reliability effects such as gate oxide integrity, electro-migration, ESD, HCI, NBTI, PBTI etc.; On-chip process, voltage, temperature, and aging sensors and monitoring; Hardware accelerators for machine learning (ML) and deep learning algorithms; Hardware implementations of ML algorithms for applications like image/object recognition, computer vision, Speech recognition, and natural language processing; ML-based intelligence in IoT under highly constrained energy/power requirements; Secure and intelligent system on chip (SoC) design for automotive, health and defense applications.
Logic and behavioral synthesis; Placement, Routing and Floor planning; CAD tools; Design automation; Hardware attacks-detection; Threat modeling & defense; Hardware-based security primitive design; Trusted design automation, Tools & Information flow.
Design verification, Test, Reliability and Fault tolerance; Formal verification; DFT; Fault modeling; Post-silicon validation; Testing memories and regular logic arrays; Design for manufacturability and yield analysis.
FPGA based combinational/sequential logic/circuit design, Hardware/Software co-design and verification; Audio, Image and video processing; Reconfigurable systems; Microcontroller, IoT and FPGA based embedded systems design; Embedded software; CAD for embedded systems; Artificial intelligence and ML based systems.
Soft copies of papers should be submitted in .pdf format as per the IEEE conference paper format, submits not exceeding six A4 size pages and paper should be uploaded through easy chair portal. There will be double blind review of the paper. Therefore do not include authors’ name in submitted paper. A Paper with authors’ names will not be considered for review. The paper must include an abstract of about 250 words and maximum of five keywords. The acceptance of the paper is based on the following factors: The purpose of the work; the manner and degree to which it advances the art; specific new results that have been obtained and their significance. Authors of the accepted papers will be informed by email. Information about necessary revisions will be communicated to the corresponding author through email. The author(s) will have to incorporate the suggestions and will have to send the revised camera ready copy of the paper in the given time limit. Along with the paper, authors are required to submit an undertaking form stating that, the paper has not been published previously, is not under consideration for publication elsewhere, and if accepted will not be published elsewhere in the same form. It is mandatory for at least one of the authors to register in non-student category for publication of the paper in proceedings. For the author presenting more than one papers, it is mandatory to register and present each paper separately.
Students, including bachelors, masters and PhDs may participate in this forum through presenting their work for better technical inputs to improve the quality of work. This forum may also provide an opportunity to the students to establish the network with industry players for job perspective.
This forum will provide the opportunities to participants to aware the various schemes/initiatives taken by several states and central government in Chip Fabrication, Electronics Manufacturing Clusters (EMC), IoT, ML and AI etc. The forum will also provide a platform to the participants to explore the funding opportunities from venture capitalist, by presenting their ideas.
The forum will provide the opportunities to the participants to accelerate the present engagement in the area of chip design and autonomous embedded systems
IEEE Consumer Electronics Society Bombay Chapter
| Particulars | Amt. in Rs. |
|---|---|
| Platinum sponsor | 3,00,000/- |
| Gold Sponsor | 2,00,000/- |
| Silver Sponsor | 1,00,000/- |
| Delegate Kit | 50,000/- |
| Technical Session Sponsorship (Per Session) | 30,000/- |
| Banner-Prime location (main stage and dining area) | 10,000/- |
| Banner- Other location | 5,000/- |
Mode of Payment |
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| Online Transfer/DD/Cheque in favour of The Registrar, Indian Institute of Technology Indore | |
| Name of the Bank | CANARA Bank, IIT Indore Campus, Simrol, Indore |
| Bank Account Number | 1476101027440 |
| IFSC Code | CNRB0006223 |
| MICR code | 452015003 |
A limited number of exhibit stalls of size 3m x 3m will be available where products can be demonstrated.
The stalls will come with a power plug and fascia. The exhibitor is expected to make arrangements for any computers or other equipment that may be needed towards the exhibit stall.
The cost of a booth will be Rs 40,000/- per stall.
Indian Institute of Technology Indore, Khandwa Rd, Simrol, Madhya Pradesh 453552
Dr. Ankur Beohar
Scientist, +91-9893383443
Mr. Sajid Khan
PhD Scholar, +91-9753171891, +91-8770075354
vdat2019[at]iiti.ac.in
